The present invention relates generally to voltage regulators, and more particularly to a switching voltage regulator at least partially implemented with flip-chip packaging.
Voltage regulators, such as DC to DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC to DC converters are particularly needed for battery management in low power devices, such as laptop notebooks and cellular phones. Switching voltage regulators (or simply xe2x80x9cswitching regulatorsxe2x80x9d) are known to be an efficient type of DC to DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage, and filtering the high frequency voltage to generate the output DC voltage. Specifically, the switching regulator includes a switch for alternately coupling and decoupling an input DC voltage source, such as a battery, to a load, such as an integrated circuit. An output filter, typically including an inductor and a capacitor, between the input voltage source and the load filters the output of the switch and thus provides the output DC voltage. The switch is typically controlled by a pulse modulator, such as a pulse width modulator or a pulse frequency modulator, which controls the switch.
Switching regulators are now being fabricated at least partially with integrated circuit techniques. Specifically, some switching regulators are being fabricated in integrated circuit chips with wire bond packaging (in which wires extend from the sides of the chip to the package, and the package has leads that are soldered to a printed circuit board). Unfortunately, one problem with wire bond chips is that they have a large parasitic inductance and resistance.
The parasitic inductance can result in large voltage transients on the integrated circuit. Specifically, although there is an abrupt change in the supply current when switching from the high to low voltage inputs, the current flowing through the parasitic inductor cannot change instantaneously. Thus, some current will continue to flow, causing the voltage on the voltage supply lines to xe2x80x9cbouncexe2x80x9d. If the voltage transients exceed the process limitations of the integrated circuit, there can be damage due to voltage overstress. In addition, if the voltages on the voltage supply lines come too close together or cross, the digital and analog circuitry in the voltage regulator will fail. Furthermore, large voltage transients create noise which can interfere with the normal operation of analog components of the power regulator. Compensating for this noise requires additional circuitry, at the expense of design time, silicon area and power consumption.
The parasitic resistance of the packaging increases energy dissipation, which wastes energy and creates excess heat. This excess heat can degrade circuit performance, and in order to avoid the degraded circuit performance, it is necessary to use expensive heat sinks or cooling systems, or limit the current flowing through the device.
In view of the foregoing, it would be advantageous to develop a switching regulator with reduced parasitic inductance and resistance.
In one aspect, the invention is directed to a voltage regulator having an input terminal and an output terminal. The voltage regulator has a printed circuit board, a substrate mounted on the printed circuit board, and a first flip-chip type integrated circuit chip mounted on the substrate. The first integrated circuit chip includes a first power switch fabricated therein to alternately couple and decouple the input terminal to the output terminal. A filter is disposed to provide a substantially DC voltage at the output terminal, and a control circuit controls the power switch to maintain the DC voltage substantially constant.
Implementations of the invention may include one or more of the following features. The power switch and filter may form a buck-converter topology. The first integrated circuit chip may be mounted on the substrate with an array of solder bumps, and the substrate may be mounted on the printed circuit board with solder balls. The flip-chip type integrated circuit chip may include a p-type region and an n-type region, and the power switch may include a plurality of p+ regions fabricated in the n-type region, and a plurality of n+ regions fabricated in the p-type region. Alternating p+ regions may be connected to the input terminal and to an intermediate terminal, and alternating n+ regions may be connected to the intermediate terminal and to ground. At least a portion of the control circuit may be fabricated in a second integrated circuit chip electrically coupled to the printed circuit board separately from the first chip. A portion of the control circuit, such as an interpreter to interpret commands from the portion of the control circuit fabricated on the second chip, or a sensor that directs measurements to the portion of the control circuit fabricated on the second chip, may be fabricated on the first chip. The filter can be electrically coupled to the printed circuit board or to the substrate separately from the first chip. The first power switch may intermittently couple an intermediate terminal to the input terminal. The first flip-chip type integrated circuit chip may have a second power switch fabricated therein to alternately couple and decouple the intermediate terminal to ground. The filter may be electrically coupled between the output terminal and the intermediate terminal. The first power switch may include a distributed array of PMOS transistors and the second power switch may include a distributed array of NMOS transistors. A rectifier may connect the intermediate terminal to ground. The rectifier may be connected to the printed circuit board separately from the first chip. The filter may include an inductor or a capacitor electrically coupling the first power switch to the output terminal. The inductor is mounted on the substrate or the printed circuit board. The capacitor may be mounted on the substrate. An input capacitor, mounted on the substrate or printed circuit board, may connect the input terminal to ground.
In another aspect, the invention is directed to an integrated circuit chip with a power switch for a voltage regulator fabricated thereon. The chip includes a substrate having a first plurality of doped regions and a second plurality of doped regions and an array of metalized pads fabricated on a surface of the substrate. The first and second pluralities of doped regions are arranged in a first alternating pattern. The array includes a first plurality of pads and a second plurality of pads, with the first and second pluralities of pads arranged in a second alternating pattern. The first plurality of pads are electrically connected to the first plurality of doped regions and to a first terminal of the voltage regulator, and the second plurality of pads are electrically connected to the second plurality of doped regions and to a second terminal in the voltage regulator.
Implementations of the invention may include one or more of the following features. The second alternating pattern may be a first set of alternating stripes, and the first alternating pattern may be a second set of alternating stripes oriented orthogonally to the first set of alternating stripes. The first and second pluralities of doped regions may be p+ regions formed in an n-type well or substrate. The first terminal may be an input terminal and the second terminal may an intermediate terminal. The first and second pluralities of doped regions may be n+ regions formed in a p-type well or substrate. The first terminal may be a ground terminal and the second terminal is an intermediate terminal. The first plurality of pads may be connected to a first plurality of solder balls and the second plurality of pads may be connected to a second plurality of solder balls interleaved with the first plurality of solder balls across a surface on the chip.
In another aspect, the invention is directed to a power switch for a voltage regulator having an input terminal and an output terminal. The power switch has a PMOS switch fabricated on a chip with a first alternating pattern of source pads and drain pads, an NMOS switch fabricated on the chip with a second alternating pattern of source pads and drain pads, and a substrate having a first signal layer with a first electrode to electrically couple the drain pads of the PMOS and NMOS switches to an intermediate terminal, a second electrode to electrically couple the source pads of the PMOS switch to the input terminal, and a third electrode to electrically couple the source pads of the NMOS switch to ground.
Implementations of the invention may include one or more of the following features. The first and second alternating patterns may be alternating rows. The first electrode may have a body and a first plurality of fingers that extend from the body toward the second electrode, the second electrode may have a body and plurality of fingers that extend toward the first electrode, and the first plurality of fingers may be interdigited with the fingers of the second electrode. The first electrode may have a second plurality of fingers that extend from the body toward the third electrode, the third electrode may have a body and a plurality of fingers that extend toward the first electrode, and the second plurality of fingers may be interdigited with the fingers of the third electrode. Each finger may overlie and be electrically coupled to a row of pads on the chip. The substrate may include a second signal layer formed on an opposite side of the substrate from the first signal layer. Conductive vias through the substrate may electrically connect the first signal layer to the second signal layer. Solder balls may electrically connect the rows of pads to the first, second and third electrodes of the first signal layer.
In another aspect, the invention is directed to a power switch for a voltage regulator. The power switch has a chip having an array of pads formed thereon and a substrate having a signal layer formed thereon. Each pad is connected to a plurality of doped regions to create a distributed array of transistors. The signal layer has a first electrode and a second electrode, the first electrode having a body and a plurality of fingers that extend from the body toward the second electrode, the second electrode having a body and plurality of fingers that extend toward the first electrode. The fingers of the first electrode are interdigited with the fingers of the second electrode and each finger overlies and is electrically coupled to a row of pads on the chip.
In another aspect, the invention is directed to a voltage regulator having a first flip-chip type integrated circuit chip mounted directly on the printed circuit board. The voltage regulator has an input terminal and an output terminal, and the first integrated circuit chip including a first power switch fabricated therein to alternately couple and decouple the input terminal to the output terminal. A filter is disposed to provide a substantially DC voltage at the output terminal, and a control circuit controls the power switch to maintain the DC voltage substantially constant.
Advantages of the invention may include the following. Device reliability, efficiency and temperature control are improved. The power switch package has a low parasitic inductance. Therefore, the package places less stress on the integrated circuit, is less likely to cause the voltages on the inputs to approach too closely, and generates less noise. The power switch package also has a low parasitic resistance, thus reducing excess heat and minimizing the loss of current flowing through the power switch package. Reducing the resistance reduces the amount of power dissipated, thereby making the switching regulator more efficient. The switching regulator can be fabricated in a flip-chip package. The package also permits the circuit density on the chip to be increased, thereby permitting lower cost, smaller area, and more complex chips.